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MP2119
2A, 6V Synchronous Step-Down Switching Regulator
The Future of Analog IC Technology
DESCRIPTION
The MP2119 is an internally compensated 1.5MHz fixed frequency PWM synchronous step-down regulator. MP2119 operates from a 2.7V to 6V input and generates an output voltage as low as 0.8V. The MP2119 integrates a 100m high-side switch and a 100m synchronous rectifier for www..com high efficiency without an external Schottky diode. With peak current mode control and internal compensation, the MP2119 based solution delivers a very compact footprint with a minimum component count. The MP2119 is available in a small 3mm x 3mm QFN package.
FEATURES
* * * * * * * * * * * * * * * * 2A Output Current Input Operation Range: 2.7V to 6V All Ceramic Capacitor Design 1.5MHz Fixed Switching Frequency Adjustable Output from 0.8V to 0.9xVIN Internal Soft-Start Frequency Synchronization Input Power Good Output Thermal Shutdown Cycle-by-Cycle Current Limiting Hiccup Short Circuit Protection 3mm x 3mm QFN Package P/ASIC/DSP/FPGA Core and I/O Supplies Printers and LCD TVs Network and Telecom Equipment Point of Load Regulators
APPLICATIONS
"MPS" and "The Future of Analog IC Technology" are Trademarks of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
VIN 2.7V to 6V 47 POK
IN POK BS SW
Efficiency vs. Output Current
100
MP2119
OFF ON
EN/SYNC GND FB
VOUT 1.8V / 2A
EFFICIENCY (%)
C3 100nF
1.2
80 60 40 20 0 0
VIN = 5V, VOUT =1.8V VIN = 3.3V, VOUT =1.8V
400
310
47
0.5 1.0 1.5 OUTPUT CURRENT (A)
2.0
MP2119 Rev. 0.93 4/16/2010
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
ORDERING INFORMATION
Part Number* MP2119DQ Package QFN10 (3mm x 3mm) Top Marking U8 Free Air Temperature (TA) -40C to +85C
* For Tape & Reel, add suffix -Z (e.g. MP2119DQ-Z). For RoHS compliant packaging, add suffix -LF (e.g. MP2119DQ-LF-Z)
PACKAGE REFERENCE
TOP VIEW
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FB GND SW IN BS
1 2 3 4 5 11 EXPOSED PAD
10 9 8 7 6
EN/SYNC GND SW IN POK
EXPOSED PAD ON BACKSIDE
ABSOLUTE MAXIMUM RATINGS (1)
IN to GND ................................... -0.3V to +6.5V SW to GND .......................... -0.3V to VIN + 0.3V SW to GND ............ -2.5V to VIN+2.5V for <50nS FB, EN/SYNC, POK to GND.......... -0.3V to +6.5V BS to SW .................................... -0.3V to +6.5V (2) Continuous Power Dissipation (TA = +25C) ..........................................................2.5W Junction Temperature ...............................150C Lead Temperature ....................................260C Storage Temperature...............-65C to +150C
Thermal Resistance
(4)
QFN10 (3mm x 3mm) .............50 ...... 12 ... C/W
Notes: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ (MAX), the junction-toambient thermal resistance JA, and the ambient temperature TA. The maximum allowable continuous power dissipation at any ambient temperature is calculated by PD (MAX) = (TJ (MAX)-TA)/JA. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. Internal thermal shutdown circuitry protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB.
JA
JC
Recommended Operating Conditions
(3)
Supply Voltage VIN .............................2.7V to 6V Output Voltage VOUT ..................0.8V to 0.9 x VIN Operating Junct. Temp (TJ)....... -40C to +85C
MP2119 Rev. 0.93 4/16/2010
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
ELECTRICAL CHARACTERISTICS (5)
VIN = VEN = 3.6V, TA = +25C, unless otherwise noted.
Parameters Supply Current Shutdown Current IN Undervoltage Lockout Threshold IN Undervoltage Lockout Hysteresis Regulated FB Voltage FB Input Current www..com EN High Threshold EN Low Threshold Internal Soft-Start Time High-Side Switch On-Resistance Low-Side Switch On-Resistance SW Leakage Current BS Under Voltage Lockout Threshold High-Side Switch Current Limit Low-Side Switch Current Limit Oscillator Frequency Maximum Synch Frequency Minimum Synch Frequency Minimum On Time Maximum Duty Cycle POK Upper Trip Threshold POK Lower Trip Threshold POK Output Voltage Low POK Deglitch Timer Thermal Shutdown Threshold Condition VEN = VIN VFB = 0.85V VEN = 0V, VIN = 5V Rising Edge Min Typ 750 1 2.59 210 TA = +25C VFB = 0.85V -40C TA +85C -40C TA +85C ISW = 300mA ISW = -300mA VEN = 0V; VIN = 5V VSW = 0V or 5V 0.776 1.6 0.4 120 100 100 -10 1.8 Sourcing Sinking TBD 1.2 3.5 3.5 1.5 2 1 50 90 10 -10 30 150 10 0.800 50 0.824 2.69 Max Units A A V mV V nA V V s m m A V A A MHz MHz MHz ns % % % V s C
1.8
FB respect to the nominal value FB respect to the nominal value ISINK = 5mA Hysteresis = 20C
0.4
Note: 5) Production test at +25C. Specifications over the temperature range are guaranteed by design and characterization.
MP2119 Rev. 0.93 4/16/2010
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
PIN FUNCTIONS
Description Feedback. This is the input to the error amplifier. An external resistive divider connects this 1 FB pin between the output and GND. The voltage on the FB pin compares to the internal 0.8V reference to set the regulation voltage. Ground. Connect these pins with larger copper areas to the negative terminals of the input 2, 9 GND and output capacitors. Switch Node Connection to the Inductor. These pins connect to the internal high and low3, 8 SW side power MOSFET switches. All SW pins must be connected together externally. Input Supply. A decoupling capacitor to ground is required close to these pins to reduce 4, 7 IN switching spikes. Bootstrap. A capacitor between this pin and SW provides a floating supply for the high-side www..com 5 BS gate driver. Open Drain Power Okay Output. "HIGH" output indicates VOUT is within 10% window. 6 POK "LOW" output indicates VOUT is out of 10% window. POK is pulled down in shutdown. Enable and Frequency Synchronization Input Pin. Forcing this pin below 0.4V shuts down 10 EN/SYNC the part. Forcing this pin above 1.6V turns on the part. Applying a 1MHz to 2MHz clock signal to this pin synchronizes the internal oscillator frequency to the external source. Exposed 11 Connect exposed pad to ground plane for optimal thermal performance. Pad Pin # Name
MP2119 Rev. 0.93 4/16/2010
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VOUT = 1.8V, TA = +25C, unless otherwise noted.
Steady State Operation
No Load VOUT 10mV/div. VOUT 10mV/div.
Steady State Operation
Half Load
Steady State Operation
Full Load
VOUT 10mV/div.
Inductor 1A/div.
Inductor 1A/div. VSW 5V/div.
Inductor 1A/div. VSW 5V/div.
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VSW 5V/div.
400ns/div
400ns/div
400ns/div
Load Transient
1A-2A Step Resistive Load
Start-up through enable
No Load
VOUT 100mV/div.
VOUT 1V/div. VPOK 2V/div.
Inductor 1A/div. VEN 2V/div. 200ns/div
MP2119 Rev. 0.93 4/16/2010
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VOUT = 1.8V, TA = +25C, unless otherwise noted.
Steady State Operation
Full Load
Shut Down through Enable
No Load
Shut Down through Enable
Full Load
VOUT 1V/div. VPOK 2V/div.
VOUT 1V/div. VOUT 1V/div. VEN 2V/div. VEN 2V/div.
VEN www..com 2V/div.
VPOK 2V/div. v 400ms/div
VPOK 2V/div. 1ms/div
Short Circut Protection
VIN=5V,VOUT=1.8V
Short Circuit Recovery
VIN=5V,VOUT=1.8V
VOUT 10mV/div. VSW 5V/div.
VOUT 1V/div. VSW 5V/div.
Inductor 1A/div. 400ns/div
Inductor 2A/div. 1ms/div
MP2119 Rev. 0.93 4/16/2010
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
FUNCTION BLOCK DIAGRAM
POK
0.88V
+ -+ --
IN EN IN
0.72V
BS
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EN/SYNC
EN/SYNC LOGIC EXCLK
EN + --
LOGIC
CLK SLOPE
PWM CURRENT COMPARATOR
SW SW
OSC
0.5pF 1.2 MEG 17pF
FB
0.8V
-+ +
COMP
SLOPE COMPENSATION AND PEAK CURRENT LIMIT
GND GND
SOFT -START
Figure 1--Function Block Diagram
MP2119 Rev. 0.93 4/16/2010
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
FUNCTIONAL DESCRIPTION
PWM Control The MP2119 is a constant frequency peakcurrent-mode control PWM switching regulator. Refer to the functional block diagram. The high side N-Channel DMOS power switch turns on at the beginning of each clock cycle. The current in the inductor increases until the PWM current comparator trips to turn off the high side DMOS switch. The peak inductor current at which the current comparator shuts off the high side power switch is controlled by the COMP voltage at the output of feedback error amplifier. The www..com transconductance from the COMP voltage to the output current is set at 11.25A/V. This current-mode control greatly simplifies the feedback compensation design by approximating the switching converter as a single-pole system. Only Type II compensation network is needed, which is integrated into the MP2119. The loop bandwidth is adjusted by changing the upper resistor value of the resistor divider at the FB pin. The internal compensation in the MP2119 simplifies the compensation design, minimizes external component counts, and keeps the flexibility of external compensation for optimal stability and transient response. Enable and Frequency Synchronization (EN/SYNC PIN) This is a dual function input pin. Forcing this pin below 0.4V for longer than 4s shuts down the part; forcing this pin above 1.6V for longer than 4s turns on the part. Applying a 1MHz to 2MHz clock signal to this pin also synchronizes the internal oscillator frequency to the external clock. When the external clock is used, the part turns on after detecting the first few clocks regardless of duty cycles. If any ON or OFF period of the clock is longer than 4s, the signal will be intercepted as an enable input and disables the synchronization. Soft-Start and Output Pre-Bias Startup When the soft-start period starts, an internal current source begins charging an internal softstart capacitor. During soft-start, the voltage on the soft-start capacitor is connected to the noninverting input of the error amplifier. The soft-start period lasts until the voltage on the soft-start capacitor exceeds the reference voltage of 0.8V.
MP2119 Rev. 0.93 4/16/2010
At this point the reference voltage takes over at the non-inverting error amplifier input. The softstart time is internally set at 120s. If the output of the MP2119 is pre-biased to a certain voltage during startup, the IC will disable the switching of both high-side and low-side switches until the voltage on the internal soft-start capacitor exceeds the sensed output voltage at the FB pin. Over current Protection The MP2119 offers cycle-to-cycle current limiting for both high-side and low-side switches. The high-side current limit is relatively constant regardless of duty cycles. When the output is shorted to ground, causing the output voltage to drop below 50% of its nominal output, the IC is shut down momentarily and begins discharging the soft start capacitor. It will restart with a full soft-start when the soft- start capacitor is fully discharged. This hiccup process is repeated until the fault is removed. Power Good Output (POK PIN) The MP2119 includes an open-drain Power Good output that indicates whether the regulator output is within 10% of its nominal output. When the output voltage moves outside this range, the POK output is pulled to ground. There is a 30s deglitch time when the POK output change its state. Bootstrap (BST PIN) The gate driver for the high-side N-channel DMOS power switch is supplied by a bootstrap capacitor connected between the BS and SW pins. When the low-side switch is on, the capacitor is charged through an internal boost diode. When the high-side switch is off and the low-side switch turns on, the voltage on the bootstrap capacitor is boosted above the input voltage and the internal bootstrap diode prevents the capacitor from discharging.
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
APPLICATION INFORMATION
Output Voltage Setting The external resistor divider sets the output voltage (see Page 1). The feedback resistor R1 also sets the feedback loop bandwidth with the internal compensation (refer to description function). The relation between R1 and feedback loop bandwidth (fC), output capacitance (CO) is as following: 1.24 x 106 R1(k) = fC (kHz) x CO (uF) The feedback loop bandwidth (fC) is no higher www..com than 1/10 of switching frequency of MP2119. In the case of ceramic capacitor as CO, it's usually set to be in the range of 50kHz and 150kHz for optimal transient performance and good phase margin. If electrolytic capacitor is used, the loop bandwidth is no higher than 1/4 of the ESR zero frequency (fESR). fESR is given by: 1 fESR = 2 x RESR x CO For example, choose fC=70kHz with ceramic capacitor, CO=47uF, R1 is estimated to be 400k. R2 is then given by: R1 R2 = VOUT -1 0.8V Table 1--Resistor Selection vs. Output Voltage Setting
VOUT (V) 1.2 1.5 1.8 2.5 3.3 R1 (k) 400 400 400 400 400 R2 (k) 806 453 316 187 127 L (H) 0.47H-1H 0.47H-1H 0.47H-1H 0.47H-1H 0.47H-1H COUT (ceramic) 47F 47F 47F 47F 47F
Inductor Selection A 0.47H to 1H inductor with DC current rating at least 25% higher than the maximum load current is recommended for most applications. For best efficiency, the inductor DC resistance shall be <10m. For most designs, the inductance value can be derived from the following equation: VOUT x (VIN - VOUT) L= VIN x IL x fOSC Where IL is Inductor Ripple Current. Choose inductor ripple current approximately 30% of the maximum load current. The maximum inductor peak current is: IL IL(MAX) = ILOAD + 2 Under light load conditions, larger inductance is recommended for improved efficiency. Input Capacitor Selection The input capacitor reduces the surge current drawn from the input and the switching noise from the device. The input capacitor impedance at the switching frequency shall be less than input source impedance to prevent high frequency switching current passing to the input source. Ceramic capacitors with X5R or X7R dielectrics are highly recommended because of their low ESR and small temperature coefficients. For most applications, a 47F capacitor is sufficient. Output Capacitor Selection The output capacitor keeps output voltage ripple small and ensures a stable regulation loop. The output capacitor impedance shall be low at the switching frequency. Ceramic capacitors with X5R or X7R dielectrics are recommended. If electrolytic capacitor is used, pay attention to output ripple voltage, extra heating, and the selection of feedback resistor R1 (refer to "Output Voltage Setting" section) due to large ESR of electrolytic capacitor.
The output ripple VOUT is approximately: VOUT VOUT x (VIN - VOUT) VIN x fOSC x L x (ESR + 1 8 x fOSC x CO )
MP2119 Rev. 0.93 4/16/2010
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
External Schottky Diode
For this part, an external schottky diode is recommended to be placed close to "SW" and "GND" pins, especially when the output current is close to 2A. With the external schottky diode, the voltage spike and negative kick on "SW" pin can be minimized; moreover, the conversion efficiency can also be improved a little. For the external schottky diode selection, it's noteworthy that the maximum reverse voltage rating of the external diode should be larger than www..com input voltage. As for the current the maximum rating of this diode, 0.5A rating should be sufficient.
PCB Layout
Top Layer
PCB layout is very important to achieve stable operation. It is highly recommended to duplicate EVB layout for optimum performance. If change is necessary, please follow these guidelines as follows. Here, the typical application circuit is taken as an example to illustrate the key layout rules should be followed. 1) For MP2119, a PCB layout with more than (or) four layers is recommended. 2) The high current paths (GND, IN and SW) should be placed very close to the device with short, direct and wide traces. 3) For MP2119, two input ceramic capacitors (2 x (10F~22F)) are strongly recommended to be placed on both sides of the MP2119 package and keep them as close as possible to the "IN" and "GND" pins. If this placement is not possible, a ceramic cap (10F~47F) must be placed across PIN7-"IN"and PIN9-"GND" since the internal Vcc supply is powered from PIN7, and good decoupling is needed to avoid any interference issues. 4) The external feedback resistors shall be placed next to the FB pin. Keep the FB trace as short as possible. Don't place test points on FB trace if possible. 5) Keep the switching node SW short and away from the feedback network.
Inner Layer1
Inner Layer2
MP2119 Rev. 0.93 4/16/2010
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
Bottom Layer
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Figure2Recommended PCB Layout of MP2119 Table 2--Suggested Surface Mount Inductors
Manufacturer Wurth Electronics
Part Number 744310055 744310095
Inductance (H) 0.55 0.95 1
Max DCR (m) 4.5 7.4 11
Current Rating (A) 14 11 6.9
Dimensions L x W x H (mm3) 7x6.9x3 7x6.9x3 8.4x8.3x4
TOKO B1015AS-1R0N
TYPICAL APPLICATION CIRCUIT
Vin 2.7V to 5.5V C1 10uF C2 10uF 6 R4 100k R3 100k 4,7 IN POK BS SW 5 3,8 D1 B0530 R2 316k C4 100nF L1 1uH Vout 1.8V/2A
MP2119
10 EN/SYNC FB GND 2,9,11 1
R1 400k
C3 47uF
Figure3Typical Application Circuit of MP2119
MP2119 Rev. 0.93 4/16/2010
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MP2119 - 2A, 6V SYNCHRONOUS STEP-DOWN SWITCHING REGULATOR
PACKAGE INFORMATION
3mm x 3mm QFN10
2.90 3.10 PIN 1 ID MARKING 0.18 0.30 2.90 3.10 0.30 0.50 1.45 1.75 PIN 1 ID SEE DETAIL A 1
10
PIN 1 ID INDEX AREA
0.50 BSC 6 5
2.25 2.55
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TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A R0.20 TYP. 0.20 REF 0.00 0.05 0.80 1.00
PIN 1 ID OPTION B R0.20 TYP.
SIDE VIEW
DETAIL A
2.90 0.70 0.25 1.70
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH. 3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX. 4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5. 5) DRAWING IS NOT TO SCALE.
2.50 0.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications.
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